1. Field of the Invention
This invention relates to computing systems, and more particularly, to reducing power consumption within clock distribution on a semiconductor chip.
2. Description of the Relevant Art
Geometric dimensions of devices and metal routes on each generation of semiconductor processor cores are decreasing. Therefore, more functionality is provided within a given area of on-die real estate. As a result, mobile devices, such as laptop computers, tablet computers, smart phones, video cameras, and the like, have increasing popularity. Typically, these mobile devices receive electrical power from a battery. Since batteries have a limited capacity, they are periodically connected to an external charger to be recharged. A vital issue for these mobile devices is power consumption. As power consumption increases, battery life for these devices is reduced and the frequency of recharging increases.
Different power modes supported by a processor core may disable portions of the chip during periods of non-use. This technique may reduce a number of switching nodes and load capacitance being switched. However, associated control logic may become complex and occupy a significant portion of the on-die real estate. Further, multiple executing applications on a mobile device may prevent sufficient disabling to significantly reduce power consumption. Reducing transistor sizes may also reduce an amount of switching capacitance. However, a limit is reached when the transistors already have the minimum available channel width. In addition, leakage current may increase with decreased transistor sizes.
Reducing the operational voltage, V, to decrease power consumption also reduces the amount of current that may flow through a transistor. Thus, the propagation delays increase through transistors. If the threshold voltages are reduced in order to turn-on the transistors sooner and aid in maintaining performance, then transistor current leakage increases, which increases power consumption. A large fraction of the total power consumption may be due to a clock distribution network. In some cases, this large fraction may be as much as half or more of the total power consumption. One or more clock signals are routed to sequential elements and memory structures across the entire die. As these clock signals toggle, buffers within the clock distribution network transition output states, consuming power in the process. Reducing the operational frequency, f, for the chip also reduces the performance of the circuits on the chip. Therefore, this reduction is generally not desirable.
In view of the above, efficient methods and mechanisms for reducing power consumption within clock distribution on a semiconductor chip are desired.